Avago Technologies LSI53C1000R - Manual (Page 260)

5-18 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Wait Reselect Instruction
If the LSI53C1000R is selected before being reselected,
it fetches the next instruction from the address pointed to
by the 32-bit jump address field stored in the
DMA Next Address (DNAD) register. Manually set the
LSI53C1000R to the target mode when it is selected.
If the LSI53C1000R is reselected, it fetches the next
instruction from the address pointed to by the
DMA SCRIPTS Pointer (DSP) register.
If the CPU sets the SIGP bit in the
Interrupt Status Zero (ISTAT0) register, the LSI53C1000R
aborts the Wait Reselect instruction and fetches the next
instruction from the address pointed to by the 32-bit jump
address field stored in the
DMA Next Address (DNAD)
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the corresponding
bits in the
SCSI Output Control Latch (SOCL) register are
set. When the target bit is set, the corresponding bit in
the
SCSI Control Zero (SCNTL0) register is also set.
When the carry bit is set, the corresponding bit in the
ALU is set.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
SCSI Output Control Latch (SOCL) register. When the
target bit is cleared, the corresponding bit in the
SCSI Control Zero (SCNTL0) register is cleared. When
the carry bit is cleared, the corresponding bit in the ALU
is cleared.
RA Relative Addressing Mode 26
When this bit is set, the 24-bit signed value in the
DMA Next Address (DNAD) register is used as a relative
displacement from the current
DMA SCRIPTS Pointer (DSP) address. Use this bit only
in conjunction with the Select, Reselect, Wait Select, and
Wait Reselect instructions. The Select and Reselect
instructions can contain an absolute alternate jump
address or a relative transfer address.