Avago Technologies LSI53C1000R - Manual (Page 161)

SCSI Registers 4-49
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
•
A SCSI gross error occurs
•
An unexpected disconnect occurs
•
A SCSI reset occurs
•
A parity error is detected
•
The handshake-to-handshake timer expires
•
The general purpose timer expires
To determine which condition(s) caused the
interrupt, read the
SCSI Interrupt Status Zero (SIST0)
and SCSI Interrupt Status One (SIST1) registers.
DIP DMA Interrupt Pending 0
This status bit is set when an interrupt condition is
detected in the DMA portion of the LSI53C1000R. The
following conditions cause a DMA interrupt to occur:
•
A PCI parity error is detected
•
A bus fault is detected
•
An abort condition is detected
•
A SCRIPTS instruction is executed in the single-step
mode
•
A SCRIPTS interrupt instruction is executed
•
An illegal instruction is detected
To determine exactly which condition(s) caused the
interrupt, read the
DMA Status (DSTAT) register.