Avago Technologies LSI53C1000R User Manual
Page 76
2-46
Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.16.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by polling
or hardware interrupts. Polling means that the microprocessor must
continually loop and read a register until it detects a bit that is set indicating
an interrupt. This method is the fastest, but it diverts CPU time from other
system tasks. The preferred method of detecting interrupts in most
systems is hardware interrupts. In this case, the LSI53C1000R asserts the
interrupt request (INTA/) line that interrupts the microprocessor, causing
the microprocessor to execute an ISR. A hybrid approach uses hardware
interrupts for long waits and polling for short waits.
The SCSI interrupt is routed to PCI Interrupt INTA/.
2.2.16.2 Registers
The registers in the LSI53C1000R used for detecting or defining interrupts
are
Interrupt Status Zero (ISTAT0)
Interrupt Status One (ISTAT1),
SCSI Interrupt Status Zero (SIST0)
SCSI Interrupt Status One (SIST1)
,
DMA Status (DSTAT), SCSI Interrupt Enable Zero (SIEN0)
SCSI Interrupt Enable One (SIEN1)
, and
Refer to the register descriptions in
for additional
information.
ISTAT – The ISTAT register includes the
Interrupt Status Zero (ISTAT0),
, and
registers. It is the only register that can be
accessed as a slave during the SCRIPTS operation. Therefore, it is the
register that is polled when polled interrupts are used. It is also the first
register that should be read after the INTA/ pin is asserted in association
with a hardware interrupt.
The INTF (Interrupt-on-the-Fly) bit should be the first interrupt serviced.
It must be written to one in order to clear it. This interrupt must be
cleared before servicing any other interrupts indicated by SIP or DIP. Do
not attempt to read the other chip status registers if the INTF bit is set,
but SIP or DIP are not set.
If the SIP bit in the
Interrupt Status Zero (ISTAT0)
register is set, then a
SCSI-type interrupt has occurred and the
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
registers should be read.