Avago Technologies LSI53C1000R - Manual (Page 254)

5-12 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
If the SCSI phase bits do not match the value stored in
the
SCSI Status One (SSTAT1) register, the
LSI53C1000R generates a phase mismatch interrupt and
the instruction is not executed.
During a Message-Out phase, after the LSI53C1000R
has performed a select with Attention (or SATN/ is
manually asserted with a Set ATN instruction), the
LSI53C1000R deasserts SATN/ during the final
SREQ/SACK/ handshake.
When the LSI53C1000R is performing a block move for
Message-In phase, it does not deassert the SACK/ signal
for the last SREQ/SACK/ handshake. Clear the
SACK/ signal using the Clear SACK I/O instruction.
SCSIP[2:0] SCSI Phase [26:24]
This field defines the desired SCSI information transfer
phase. When the LSI53C1000R operates in the initiator
mode, these bits are compared with the latched SCSI
phase bits in the
SCSI Status One (SSTAT1) register.
When the LSI53C1000R operates in the target mode, it
asserts the phase defined in this field. The following table
describes the possible combinations and the
corresponding SCSI phase.
MSG C_D I_O SCSI Phase
0 0 0 ST Data-Out
0 0 1 ST Data-In
0 1 0 Command
0 1 1 Status
1 0 0 DT Data-Out
1 0 1 DT Data-In
1 1 0 Message-Out
1 1 1 Message-In