Avago Technologies LSI53C1000R User Manual
Page 77
SCSI Functional Description
2-47
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
If the DIP bit in the
Interrupt Status Zero (ISTAT0)
register is set, then a
DMA-type interrupt has occurred and the
register
should be read.
SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set. To avoid missing a SCSI
interrupt, the SIST0 and SIST1 registers should be read before the
DSTAT register is read.
When set, the SIRQD bit in ISTAT1 disables the INTA/ pin for the SCSI
function. The interrupt is not lost or ignored but is merely masked at the
pin. If the INTA/ pin is already asserted when SIRQD is set, the INTA/
pin remains asserted until the interrupt is serviced. Future interrupts are
masked at the pin until SIRQD is cleared.
Note that the host can read ISTAT as the SCRIPTS code is writing to
ISTAT. In this case the data is unstable, so the read should be retried.
SIST0 and SIST1 – The
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
registers contain the status of
SCSI-type interrupts whether they are enabled in
SCSI Interrupt Enable Zero (SIEN0)
and
SCSI Interrupt Enable One (SIEN1)
or not. Reading these registers
determines the conditions that caused the SCSI-type interrupt, clears
any bits that are set in SIST0 and SIST1, and clears the SIP bit in
Interrupt Status Zero (ISTAT0)
. Because the LSI53C1000R stacks
interrupts, SIST0 and SIST1 are not necessarily cleared after a read;
additional interrupts may still be pending.
If the LSI53C1000R is receiving data from the SCSI bus and a fatal
interrupt condition occurs, the chip attempts to send the contents of the
DMA FIFO to memory before generating the interrupt. Reading
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
clears the CRC Error bit (bit 7) in the
register.
If the LSI53C1000R is sending data to the SCSI bus and a fatal SCSI
interrupt condition occurs, data could remain in the DMA FIFO. To
determine if the DMA FIFO is empty, check the DMA FIFO Empty (DFE)
bit in
register. If this bit is cleared, set the