Avago Technologies LSI53C1000R - Manual (Page 306)

6-24 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
6.4.2 Initiator Timing
Tables 6.23 through 6.30 and figures 6.17 and 6.24 describe Initiator timing.
Table 6.23 Nonburst Opcode Fetch, 32-Bit Address and Data
Symbol Parameter
66 MHz PCI 33 MHz PCI
Unit Min Max Min Max
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns
t
4
Side signal input setup time 5 – 10 – ns
t
5
Side signal input hold time 0 – 0 – ns
t
6
CLK to side signal output valid 2 6 2 12 ns