Avago Technologies LSI53C1000R - Manual (Page 371)

B-3
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Memory
CK
Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of
fast memory (150 ns devices @ 66 MHz). The HCT374s may be replaced with HCT377s.
Optional – for Flash Memory only,
not required for EEPROMs.
D[3:0] Q[3:0]
MAD[3:0]
Bus
E
27C512-15/
MOE/
OE
MCE/
CE
GPIO4
MWE/
+ 12 V VPP
WE
28F512-15/
Socket
LSI53C1000R
D[7:0]
CK
Q[7:0]
A[7:0]
QE
D[7:0]
CK
Q[7:0]
QE
A[15:8]
8
V
DD
MAS0/
MAS1/
8
HCT374
HCT374
D[7:0]
MAD3 4.7 K
8
8
VPP
Control
MAD[7:0]
Bus
QE
A[19:16]
4
HCT377
4