Avago Technologies LSI53C1000R - Manual (Page 33)

PCI Functional Description 2-3
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.1 PCI Functional Description
The LSI53C1000R is a PCI to Ultra160 SCSI Controller.
2.1.1 PCI Addressing
There are three physical address spaces defined in the PCI specification:
•
PCI Configuration space
•
I/O space for operating registers
•
Memory space for operating registers
2.1.1.1 Configuration Space
The host processor uses this configuration space to initialize the
LSI53C1000R. A configuration space register is defined for the SCSI
function. The configuration register is initialized by the system BIOS
using PCI configuration cycles. The configuration space is a contiguous
256 x 8-bit set of addresses. Decoding C_BE[3:0]/ determines if a PCI
cycle is intended to access the configuration register space. The IDSEL
bus signal is a “chip select” that allows access to the configuration
register space only. A configuration read/write cycle without IDSEL is
ignored. The host processor uses the eight lower order address bits
(AD[7:0]) to select a specific 8-bit register. Bits AD[10:8] decode the
SCSI function configuration register (AD[10:8] = 0b000).
Table 4.1 on
page 4-2 is an illustration of the PCI Configuration Register Map.
At initialization time, each PCI device is assigned a base address for
memory and I/O accesses. In the LSI53C1000R, the upper 24 bits of the
address are selected. On every access, the LSI53C1000R compares its
assigned base addresses with the value on the Address/Data bus during
the PCI address phase. If the upper 24 bits match, the access is
designated for the LSI53C1000R. The low order eight bits define the
register to be accessed. A decode of C_BE[3:0]/ determines which
register and what type of access is performed.