Avago Technologies LSI53C1000R User Manual
Page 187
SCSI Registers
4-75
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Note:
Checking for this condition can be disabled by setting the
DCRC bit in the CRCCNTL0 register.
•
An illegal Force CRC Request Block Move is
executed.
•
A SCRIPTS RAM parity error.
Note:
The
register indicates which
condition caused an SGE SCSI interrupt. This register is
shadowed behind the
SCSI Interrupt Status Zero (SIST0)
register. It can be accessed by setting bit 7, the
Enable Shadowed SGE Register (ShSGE) bit, in the
register.
UDC
Unexpected Disconnect
2
This bit is set when the LSI53C1000R is operating in the
initiator mode and the target device unexpectedly
disconnects from the SCSI bus. This bit is only valid when
the LSI53C1000R operates in the initiator mode. When the
LSI53C1000R operates in the low level mode, any
disconnect causes an interrupt, even a valid SCSI
disconnect. This bit is also set if a selection time-out
occurs. Because a selection time-out is not considered an
expected disconnect, an unexpected disconnect may occur
before, at the same time, or stacked after the STO interrupt.
RST
SCSI RST/ Received
1
This bit is set when the LSI53C1000R detects an active
SRST/ signal, whether the reset is generated external to
the chip or caused by the Assert SRST/ bit in the
register. This SCSI reset
detection logic is edge-sensitive, so that multiple
interrupts are not generated for a single assertion of the
SRST/ signal.
PAR
Parity/CRC/AIP Error
0
This bit indicates the LSI53C1000R detected a
Parity/CRC/AIP error while receiving or sending SCSI
data. Refer to the Disable Halt on Parity/CRC/AIP Error
or ATN/ condition bit in the
register for more information about when this condition
actually is raised.