Avago Technologies LSI53C1000R User Manual
Page 176
4-64
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
This function is useful for memory-to-register operations
using the Memory Move instruction when an
LSI53C1000R is I/O mapped. Bits 4 and 5 of the
register determine the
configuration status of the LSI53C1000R.
ERL
Enable Read Line
3
This bit enables a PCI Read Line command. If this bit is
set and the chip is about to execute a read cycle
(other than an opcode fetch), the command is 0b1110.
ERMP
Enable Read Multiple
2
If this bit is set and cache mode is enabled, a
Read Multiple command is used on all read cycles when
it is legal.
BOF
Burst Opcode Fetch Enable
1
Setting this bit causes the LSI53C1000R to fetch
instructions in burst mode. Specifically, the chip bursts in
the first two Dwords of all instructions using a single bus
ownership. If the instruction is a Memory-to-Memory
Moves type, the third Dword is accessed in a subsequent
bus ownership. If the instruction is an indirect type, the
additional Dword is accessed in a subsequent bus
ownership. If the instruction is a table indirect block move
type, the chip accesses the remaining two Dwords in a
subsequent bus ownership, thereby fetching the four
Dwords required in two bursts of two Dwords each. If
prefetch is enabled, this bit has no affect. This bit also
has no affect on fetches out of SCRIPTS RAM.
MAN
Manual Start Mode
0
Setting this bit prevents the LSI53C1000R from
automatically fetching and executing SCSI SCRIPTS
when the
register is
written. When this bit is set, the Start DMA bit in the
register must be set to begin
SCRIPTS execution. Clearing this bit causes the
LSI53C1000R to automatically begin fetching and
executing SCSI SCRIPTS when the
register is written. This bit
normally is not used for SCSI SCRIPTS operations.