Avago Technologies LSI53C1000R - Manual (Page 328)

6-46 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.26 External Memory Write
CLK
(Driven by System)
PAR
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000R)
STOP/
(Driven by LSI53C1000R)
DEVSEL/
(Driven by LSI53C1000R)
AD[31:0]
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
1 2 3 4 5 6 7 8 9 10
Addr
In
MAD
(Driven by LSI53C1000R)
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C1000R)
MAS0/
(Driven by LSI53C1000R)
MCE/
(Driven by LSI53C1000R)
MOE/
(Driven by LSI53C1000R)
MWE/
(Driven by LSI53C1000R)
t
1
t
2
t
1
t
2
CMD
In
t
1
t
2
t
1
t
2
t
1
t
13
t
11 t
12
Data In
t
2
t
1
Byte Enable
t
2
In
t
1
t
2
t
2
t
3
t
3
t
3
(Driven by Master)
(Driven by Master)
t
23