Avago Technologies LSI53C1000R - Manual (Page 45)

PCI Functional Description 2-15
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Read Example 2 – Burst = 8 Dwords; Cache Line Size = 4 Dwords:
Read Example 3 – Burst = 16 Dwords; Cache Line Size = 8 Dwords:
A to B: MRL (6 bytes)
A to C: MRL (13 bytes)
A to D: MRM (17 bytes)
C to D: MRM (5 bytes)
C to E: MRM (21 bytes)
D to F: MRM (32 bytes)
A to H: MRM (32 bytes)
MRM (32 bytes)
MRM (17 bytes)
A to G: MRM (32 bytes)
MRM (32 bytes)
MR (2 bytes)
A to B: MRL (6 bytes)
A to C: MRL (13 bytes)
A to D: MRL (17 bytes)
C to D: MRL (5 bytes)
C to E: MRM (21 bytes)
D to F: MRM (32 bytes)
A to H: MRM (64 bytes)
MRL (17 bytes)
A to G: MRM (64 bytes)
MR (2 bytes)