Registers: 0x5c–0x5f – Avago Technologies LSI53C1000R User Manual
Page 239
SCSI Shadow Registers
4-127
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
register is shadowed behind the
SCSI Interrupt Status One (SIST1)
register. It can be accessed by setting bit 7, the Enable Shadowed
SGE Register (ShSGE) bit, in the
register.
R
Reserved
[7:6]
PNCRC
Pad Request with no CRC Request Following
5
FCRC
Force CRC
4
DTST
Switch from DT to ST timings during a transfer
3
NFCRC
Phase Change with no final CRC Request
2
MCRC
Multiple CRC Requests with the same offset
1
R
Reserved
0
Registers: 0x5C–0x5F
Shadowed Scratch Register B (SCRATCHB)
Read/Write
SCRATCHB
Scratch Register B
[31:0]
When the PCI Configuration Info Enable bit in the
register is set, SCRATCH
Register B is placed in the shadow mode. In this mode,
bits [31:13] of the
register return bits [31:13] of the PCI
Base Address Register Three (BAR3) (SCRIPTS RAM)
Bits [12:0] of SCRATCH B always return zeros. Writes to
the SCRATCH B register have no effect. Resetting the
PCI Configuration Info Enable bit causes the
SCRATCH B register to return to normal operation.
31
0
SCRATCHB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0