Avago Technologies LSI53C1000R - Manual (Page 74)

2-44 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
To configure the LSI53C1000R for Ultra160 DT transfers, perform the
following steps:
Step 1. Enable the SCSI Clock Quadrupler – The LSI53C1000R can
quadruple the frequency of a 40 MHz SCSI clock, allowing the
system to perform Ultra160 SCSI transfers. This option is
user-selectable through bit settings in the
SCSI Test One (STEST1) register. At power-up or reset, the
quadrupler is disabled and powered down. Follow the steps in
the bit description to enable the clock quadrupler.
Step 2. Program the Transfer Rate – Using SCNTL3 and SCNTL4,
program the register to 160 Mbytes/s transfer rate.
Step 3. Program the Maximum SCSI Offset – Using SXFER, program
the maximum SCSI DT Synchronous offset to 0x3E.
Step 4. Enable the TolerANT technology – Set the TolerANT Enable bit,
SCSI Test Three (STEST3) , bit 7. Active negation must be
enabled for the LSI53C1000R to perform Ultra160 SCSI
transfers.
Figure 2.5 illustrates the clock division factors used in each register as
well as the role of the register bits in determining the transfer rate. An
example of configuring the Ultra160 SCSI transfer speed is:
1. Set SCNTL3 to 0x18.
2. Set SXFER to 0x3E.
3. Set SCNTL4 to 0x80.
These settings program the LSI53C1000R SCSI clock to send and
receive at 160 MHz with a synchronous SCSI offset of 0x3E.