Avago Technologies LSI53C1000R User Manual
Page 38
2-8
Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
size based on the amount of data to transfer. The maximum allowable
burst size is determined from the
burst size bits
and the
register, bit 2.
2.1.2.11 Dual Address Cycles (DACs) Command
When 64-bit addressing is required, the LSI53C1000R performs DACs,
according to the PCI 2.2 specification. If any of the selector registers
contain a nonzero value, a DAC is generated.
2.1.2.12 Memory Read Line Command
This command is identical to the Memory Read command, except it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data
transfers where the memory system and the requesting master might
gain some performance advantage by reading to a cache line boundary
rather than a single memory cycle. The Read Line function in the
LSI53C1000R takes advantage of the PCI 2.2 specification regarding
issuance of this command.
If the cache mode is disabled, no Read Line commands are issued.
If the cache mode is enabled, a Read Line command is issued on all
read cycles, except nonprefetch opcode fetches, when the following
conditions are met:
•
The CLSE bit (Cache Line Size Enable, bit 7, of the
register) is set.
•
The ERL bit (Enable Read Line, bit 3, of the
register) is set.
•
The
register must contain a legal burst size
value (8, 16, 32, 64, or 128 Dwords) that is less than or equal to the
DMODE burst size.
•
The transfer crosses a Dword boundary but not a cache line boundary.
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.