Avago Technologies LSI53C1000R - Manual (Page 252)

5-10 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
OPC Opcode 27
This 1-bit field defines the instruction to execute as a
block move (MOVE).
Target Mode
The LSI53C1000R verifies that it is connected to the
SCSI bus as a target before executing this instruction.
The LSI53C1000R asserts the SCSI phase signals
(SMSG/, SC_D/, and SI_O/) as defined by the
Phase Field bits in the instruction.
If the instruction is for the command phase, the
LSI53C1000R receives the first command byte and
decodes its SCSI Group Code.
•
If the SCSI Group Code is either Group 0,
Group 1, Group 2, or Group 5, then the LSI53C1000R
overwrites the
DMA Byte Counter (DBC) register with
the length of the Command Descriptor Block: 6, 10, or
12 bytes.
•
If the Vendor Unique Enhancement 0 (VUE0) bit
(
SCSI Control Two (SCNTL2) , bit 1) is cleared and the
SCSI group code is a vendor unique code, the
LSI53C1000R overwrites the
DMA Byte Counter (DBC)
register with the length of the Command Descriptor
Block: 6, 10, or 12 bytes. If the VUE0 bit is set, the
LSI53C1000R receives the number of bytes in the byte
count regardless of the group code.
•
If any other Group Code is received, the
DMA Byte Counter (DBC) register is not modified and
the LSI53C1000R requests the number of bytes
specified in the
DMA Byte Counter (DBC) register. If
the DBC register contains 0x000000, an illegal
instruction interrupt is generated.
The LSI53C1000R transfers the number of bytes
specified in the
DMA Byte Counter (DBC) register
starting at the address specified in the
DMA Next Address (DNAD) register. If the Opcode bit is
set and a data transfer ends on an odd byte boundary,
OPC Instruction Defined
0 MOVE/MOVE64
1 CHMOV/CHMOV64