Altera POS-PHY Level 2 and 3 Compiler - Manual (Page 34)

3–6 Chapter 3: Functional Description
OpenCore Plus Time-Out Behavior
POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation
Preliminary
Packet Data Width Conversion
Packet data width conversion provides conversion from a narrower to a wider data
stream, and from a wider to a narrower data stream, if required (such as, 8-bit to 32-
or 16-bit, or 32-bit to 8- or 16-bit, and so on).
Packet FIFO Buffer
The packet FIFO buffer has configurable width, depth, and fill level options. The FIFO
buffer stores packet data in line with its associated packet flags (start of packet (SOP),
end of packet (EOP), modulo (mod), and so on.
‘B’ Interface
The ‘B’ interface can be positioned at four different places, as follows:
1. After the first data width conversion—you provide a FIFO-like interface. The data
width must be greater than or equal to the required POS-PHY bus width. Atlantic ™
interfaces here can only be masters.
2. After the packet FIFO buffer—you must interface to the internal packet FIFO
buffer at the data width of the FIFO buffer, which is greater than or equal to that of
the required POS-PHY bus. Atlantic interfaces here can be master or a slave
interfaces.
3. After the second data width conversion—this position provides an interface where
the data width can be narrower than that supported by the FIFO buffer. For
example, a 32-bit POS-PHY to or from an 8-bit POS-PHY. Atlantic interfaces here
can be a master or a slave interfaces.
4. After a POS-PHY interface—where you can create a POS-PHY bridge. From a
single compiler you can build a MPHY to multiple SPHY bridge, or an SPHY to
SPHY bridge. You can create more complex solutions by instantiating more than
one MegaCore function.
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation supports the following two operation modes:
■ Untethered—the design runs for a limited time.
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior may be masked by the time-out behavior of
the other megafunctions.
1
For MegaCore functions, the untethered timeout is 1 hour; the tethered timeout value
is indefinite.
Your design stops working after the hardware evaluation time expires and the
following events occur: