Altera Stratix V Avalon-ST - Manual (Page 113)

Bit(s) Field Description
[6:4]
multiple message
enable
This field indicates permitted values for MSI signals. For example,
if “100” is written to this field 16 MSI signals are allocated.
• 3’b000: 1 MSI allocated
• 3’b001: 2 MSI allocated
• 3’b010: 4 MSI allocated
• 3’b011: 8 MSI allocated
• 3’b100: 16 MSI allocated
• 3’b101: 32 MSI allocated
• 3’b110: Reserved
• 3’b111: Reserved
[3:1]
multiple message
capable
This field is read by system software to determine the number of
requested MSI messages.
• 3’b000: 1 MSI requested
• 3’b001: 2 MSI requested
• 3’b010: 4 MSI requested
• 3’b011: 8 MSI requested
• 3’b100: 16 MSI requested
• 3’b101: 32 MSI requested
• 3’b110: Reserved
[0]
MSI Enable
If set to 0, this component is not permitted to use MSI.
Related Information
• PCI Express Base Specification 2.1 or 3.0
• PCI Local Bus Specification, Rev. 3.0
Hard IP Reconfiguration Interface
The Hard IP reconfiguration interface is an Avalon-MM slave interface with a 10-bit address and 16-bit
data bus. You can use this bus to dynamically modify the value of configuration registers that are read-
only at run time. To ensure proper system operation, reset or repeat device enumeration of the PCI
Express link after changing the value of read-only configuration registers of the Hard IP.
For an example that illustrates how to use this interface, refer to PCI SIG Gen2 x8 Merged Design - Stratix
V on the Altera wiki. The Related Information section below provides a link to this example.
UG-01097_avst
2014.12.15
Hard IP Reconfiguration Interface 5-61
Interfaces and Signal Descriptions Altera Corporation
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