Altera Stratix V Avalon-ST - Manual (Page 201)

Related Information
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer on page 7-3
SDC Timing Constraints
You must include component-level Synopsys Design Constraints (SDC) timing constraints for the
Stratix V Hard IP for PCI Express IP Core and system-level constraints for your complete design. The
example design that Altera describes in the Testbench and Design Example chapter includes the
constraints required for the for Stratix V Hard IP for PCI Express IP Core and example design. The file,
<install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altpcied_sv.sdc , includes both the component-level
and system-level constraints. In this example, you should only apply the first two constraints, to derive
PLL clocks and clock uncertainty, once across all of the SDC files in your project. Differences between
Fitter timing analysis and TimeQuest timing analysis arise if these constraints are applied more than once.
This example shows constraints for three components:
• Stratix V Hard IP for PCI Express IP Core
• Transceiver Reconfiguration Controller IP Core
• Transceiver PHY Reset Controller IP Core
The .sdc file also specifies some false timing paths for Transceiver Reconfiguration Controller and
Transceiver PHY Reset Controller IP Cores. Be sure to include these constraints in your .sdc file.
Note: You may need to change the name of the Reconfiguration Controller clock,
reconfig_xcvr_clk
,
to match the clock name used in your design. The following error message indicates that
TimeQuest could not match the constraint to any clock in your design:
Ignored filter at altpcied_sv.sdc(25): *reconfig_xcvr_clk* could not be matched
with a port or pin or register or keeper or net
Example 13-1: SDC Timing Constraints Required for the Stratix V Hard IP for PCIe and Design
Example
# Constraints required for the Hard IP for PCI Express
# derive_pll_clock is used to calculate all clock derived from
# PCIe refclk. It must be applied once across all of the SDC
# files used in a project
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
#########################################################################
# Reconfig Controller IP core constraints
# Set reconfig_xcvr clock:
# this line will likely need to be modified to match the actual
# clock pin name used for this clock, and also changed to have
# the correct period set for the clock actually used
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}
{*reconfig_xcvr_clk*}
######################################################################
# Hard IP testin pins SDC constraints
set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
######################################################################
# These additional constraints are for Gen3 only
UG-01097_avst
2014.12.15
SDC Timing Constraints 13-3
Design Implementation Altera Corporation
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