Altera Stratix V Avalon-ST - Manual (Page 221)

Memory BAR Mapping
Expansion ROM BAR Not implemented by design example; behavior is unpredictable.
I/O Space BAR (any) Not implemented by design example; behavior is unpredictable.
Chaining DMA Control and Status Registers
The software application programs the chaining DMA control register located in the Endpoint applica‐
tion. The following table describes the control registers which consists of four dwords for the DMA write
and four dwords for the DMA read. The DMA control registers are read/write.
In this table, Addr specifies the Endpoint byte address offset from BAR2 or BAR3.
Table 17-2: Chaining DMA Control Register Definitions
Addr Register Name Bits[31:]24 Bit[23:16] Bit[15:0]
0x0 DMA Wr Cntl DW0 Control Field Number of descriptors in
descriptor table
0x4 DMA Wr Cntl DW1 Base Address of the Write Descriptor Table (BDT) in the RC Memory–
Upper DWORD
0x8 DMA Wr Cntl DW2 Base Address of the Write Descriptor Table (BDT) in the RC Memory–
Lower DWORD
0xC DMA Wr Cntl DW3 Reserved Reserved RCLAST–Idx of last
descriptor to process
0x10 DMA Rd Cntl DW0 Control Field (described in the next table) Number of descriptors in
descriptor table
0x14 DMA Rd Cntl DW1 Base Address of the Read Descriptor Table (BDT) in the RC Memory–
Upper DWORD
0x18 DMA Rd Cntl DW2 Base Address of the Read Descriptor Table (BDT) in the RC Memory–
Lower DWORD
0x1C DMA Rd Cntl DW3 Reserved Reserved RCLAST–Idx of the last
descriptor to process
The following table describes the control fields of the of the DMA read and DMA write control registers.
17-10 Chaining DMA Control and Status Registers
UG-01097_avst
2014.12.15
Altera Corporation Testbench and Design Example
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