Altera Stratix V Avalon-ST - Manual (Page 44)

Base and Limit Registers for Root Ports
Table 4-3: Base and Limit Registers
The following table describes the
Base
and
Limit
registers which are available in the Type 1 Configuration Space
for Root Ports. These registers are used for TLP routing and specify the address ranges assigned to components
that are downstream of the Root Port or bridge.
Parameter Value Description
Input/
Output
Disabled
16-bit I/O addressing
32-bit I/O addressing
Specifies the address widths for the
IO base
and
IO
limit
registers.
Prefetchable
memory
Disabled
16-bit memory addressing
32-bit memory addressing
Specifies the address widths for the
Prefetchable
Memory Base
register and
Prefetchable Memory
Limit
register.
Related Information
PCI to PCI Bridge Architecture Specification
Device Identification Registers
Table 4-4: Device ID Registers
The following table lists the default values of the read-only Device ID registers. You can use the parameter editor
to change the values of these registers. Refer to Type 0 Configuration Space Registers for the layout of the Device
Identification registers.
Register Name Range Default Value Description
Vendor ID 16 bits 0x00000000 Sets the read-only value of the
Vendor ID
register. This
parameter cannot be set to 0xFFFF, per the PCI Express
Specification.
Address offset: 0x000.
Device ID 16 bits 0x00000001 Sets the read-only value of the
Device ID
register. This
register is only valid in the Type 0 (Endpoint) Configu‐
ration Space.
Address offset: 0x000.
Revision ID 8 bits 0x00000001 Sets the read-only value of the
Revision ID
register.
Address offset: 0x008.
UG-01097_avst
2014.08.18
Base and Limit Registers for Root Ports 4-7
Parameter Settings Altera Corporation
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