Altera Stratix V Avalon-ST - Manual (Page 20)

Understanding Physical Placement of the PCIe IP Core
For more information about physical placement of the PCIe blocks, refer to the links below. Contact your
Altera sales representative for detailed information about channel and PLL usage.
Related Information
Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices on page 5-69
Compiling the Design in the Qsys Design Flow
To compile the Qsys design example in the Quartus II software, you must create a Quartus II project and
add your Qsys files to that project.
1. Before compiling, you can optionally turn on two parameters in the testbench. The first parameter
specifies pin assignments that match those for the Altera Development Kit board I/Os. The second
parameter enables the Compliance Base Board (CBB) logic on the development board. In the Gen1 x8
example design, complete the following steps if you want to enable these parameters:
a. Right-click the APPS component and select Edit.
b. Turn on Enable FPGA Dev kit board I/Os.
c. Turn on Enable FPGA Dev kit board CBB logic.
d. Click Finish.
e. On the Generate menu, select Generate Testbench System and then click Generate.
f. On the Generate menu, select Generate HDL and then click Generate. (You can use the same
parameters that are specified in Generating the Testbench earlier in this chapter).
2. In the Quartus II software, click the New Project Wizard icon.
3. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you
previously turned it off.)
4. On the Directory, Name, Top-Level Entity page, enter the following information:
a. The working directory shown is correct. You do not have to change it.
b. For the project name, browse to the synthesis directory that includes your Qsys project,
<working_dir>/pcie_de_gen1_x8_ast128/synthesis . Select your variant name,
pcie_de_gen1_x8_ast128.v . Then, click Open.
c. For Project Type select Empty project.
5. Click Next to display the Add Files page.
6. Complete the following steps to add the Quartus II IP File ( .qip )to the project:
a. Click the browse button. The Select File dialog box appears.
b. In the Files of type list, select IP Variation Files (*.qip *.sip).
c. Click pcie_de_gen1_x8_ast128.qip and then click Open.
d. On the Add Files page, click Add.
7. Click Next to display the Device page.
8. On the Family & Device Settings page, choose the following target device family and options:
a. In the Family list, select Stratix V (GS/ST/GX/E).
b. In the Devices list, select Stratix V GX PCIe.
c. In the Available Devices list, select 5SGXEA7K2F40C2 .
9. Click Next to close this page and display the EDA Tool Settings page.
2-6 Understanding Physical Placement of the PCIe IP Core
UG-01097_avst
2014.12.15
Altera Corporation Getting Started with the Stratix V Hard IP for PCI Express
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