Altera Stratix V Avalon-ST User Manual

Page 15

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Getting Started with the Stratix V Hard IP for

PCI Express

2

2014.12.15

UG-01097_avst

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This section provides instructions to help you quickly customize, simulate, and compile the Stratix V

Hard IP for PCI Express IP Core. When you install the Quartus II software you also install the IP Library.

This installation includes design examples for Hard IP for PCI Express under the

<install_dir>/ip/altera/

altera_pcie/

directory.

After you install the Quartus II software, you can copy the design examples from the

<install_dir>/ip/altera/

altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/<dev>

directory. This walkthrough uses the

Gen1 ×8 Endpoint, pcie_de_gen1_x8_ast128.qsys. The following figure illustrates the top-level modules

of the testbench in which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine, labeled APPS

in the following figure, and a Root Port model. The simulation can use the parallel PHY Interface for PCI

Express (PIPE) or serial interface.

Figure 2-1: Testbench for an Endpoint

APPS

altpcied_<dev>_hwtcl.v

Hard IP for PCI Express Testbench for Endpoints

Avalon-ST TX

Avalon-ST RX

reset

status

Avalon-ST TX

Avalon-ST RX

reset

status

DUT

altpcie_<dev>_hip_ast_hwtcl.v

Root Port Model

altpcie_tbed_<dev>_hwtcl.v

PIPE or

Serial

Interface

Root Port BFM

altpcietb_bfm_rpvar_64b_x8_pipen1b

Root Port Driver and Monitor

altpcietb_bfm_vc_intf

Note: The Quartus II release automatically creates a simulation log,

altpcie_monitor_<dev>_dlhip_tlp_file_

log.log

, file in your simulation directory. If you have an existing 13.1 or older design, you must

regenerate it in the current release in order to simulate. Regeneration is necessary to create the

supporting monitor file the generates

altpcie_monitor_<dev>_dlhip_tlp_file_log.log

. Refer to

Understanding Simulation Log File Generation for details.

Altera provides example designs to help you get started with the Stratix V Hard IP for PCI Express IP

Core. You can use example designs as a starting point for your own design. The example designs include

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are

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trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html

. Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

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