Altera Stratix V Avalon-ST User Manual
Page 65
Figure 5-10: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with non-
Qword Aligned Addresses
The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for TLPs
with a 3 dword header and non-qword aligned addresses. In this case, bits[127:96] represent Data0
because address[2] in the TLP header is set. The assertion of
rx_st_empty
in a
rx_st_eop
cycle indicates
valid data on the lower 64 bits of
rx_st_data
.
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_empty
Data0
Data 4
Header 2
Data 3
Header 1
Data 2
Data (n)
Header 0
Data 1
Data (n-1)
pld_clk
Figure 5-11: 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLPs with non-Qword
Aligned Addresses
The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for a four
dword header with non-qword aligned addresses. In this example,
rx_st_empty
is low because the data is
valid for all 128 bits in the
rx_st_eop
cycle.
pld_clk
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_empty
Header 3
Data 2
Header 2
Data 1
Data n
Header 1
Data 0
Data n-1
Header 0
Data n-2
UG-01097_avst
2014.12.15
Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
5-13
Interfaces and Signal Descriptions
Altera Corporation