Altera Stratix V Avalon-ST - Manual (Page 90)

Signal Direction Description
• 11011: Recovery.Equalization, Phase 0
• 11100: Recovery.Equalization, Phase 1
• 11101: Recovery.Equalization, Phase 2
• 11110: recovery.Equalization, Phase 3
Related Information
• PCI Express Card Electromechanical Specification 2.0
• Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
ECRC Forwarding
On the Avalon-ST interface, the ECRC field follows the same alignment rules as payload data. For packets
with payload, the ECRC is appended to the data as an extra dword of payload. For packets without
payload, the ECRC field follows the address alignment as if it were a one dword payload. The position of
the ECRC data for data depends on the address alignment. For packets with no payload data, the ECRC
position corresponds to the position of
Data0
.
Error Signals
The following table describes the ECC error signals. These signals are all valid for one clock cycle. They
are synchronous to
coreclkout_hip
.
ECC for the RX and retry buffers is implemented with MRAM. These error signals are flags. If a specific
location of MRAM has errors, as long as that data is in the ECC decoder, the flag indicates the error.
When a correctable ECC error occurs, the Stratix V Hard IP for PCI Express recovers without any loss of
information. No Application Layer intervention is required. In the case of uncorrectable ECC error,
Altera recommends that you reset the core.
The Avalon-ST
rx_st_err
indicates an uncorrectable error in the RX buffer. This signal is described in
64-, 128-, or 256-Bit Avalon-ST RX Datapath in the Avalon-ST RX Interface description.
Table 5-8: Error Signals
Signal I/O Description
derr_cor_ext_rcv0
Output Indicates a corrected error in the RX buffer. This signal is for
debug only. It is not valid until the RX buffer is filled with data.
This is a pulse, not a level, signal. Internally, the pulse is
generated with the 500 MHz clock. A pulse extender extends the
signal so that the FPGA fabric running at 250 MHz can capture
it. Because the error was corrected by the IP core, no Application
Layer intervention is required. (1)
5-38 ECRC Forwarding
UG-01097_avst
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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