Altera Stratix V Avalon-ST - Manual (Page 78)

Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}
Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}
Figure 5-22: 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-Dword Header with Non-Qword
Aligned Address
pld_clk
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
Header 1 Header3 Data0 Data2
Header 0 Header2 Data1
Figure 5-23: 64-Bit Transaction Layer Backpressures the Application Layer
The following figure illustrates the timing of the TX interface when the Stratix V Hard IP for PCI Express
pauses transmission by the Application Layer by deasserting
tx_st_ready
. Because the
readyLatency
is
two cycles, the Application Layer deasserts
tx_st_valid
after two cycles and holds
tx_st_data
until two
cycles after
tx_st_ready
is asserted.
coreclkout
tx_st_sop
tx_st_eop
tx_st_ready
tx_st_valid
tx_st_err
tx_st_data[63:0] . . . . . . . . . .
readyLatency
00. . 00 ... BB... BB ... BBBB0306BBB0305 BB... BB.. BB ... BB ... BB ... BB ... BB... .
5-26 Data Alignment and Timing for the 64‑Bit Avalon‑ST TX Interface
UG-01097_avst
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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