Altera Stratix V Avalon-ST - Manual (Page 152)

Clock Summary
Table 7-4: Clock Summary
Name Frequency Clock Domain
coreclkout_hip 62.5, 125 or 250 MHz Avalon-ST interface between the Transaction and
Application Layers.
pld_clk 62.5, 125, or 250 MHz Application and Transaction Layers.
refclk
100 or 125 MHz SERDES (transceiver). Dedicated free running input
clock to the SERDES block.
reconfig_xcvr_clk 100 –125 MHz Transceiver Reconfiguration Controller.
hip_reconfig_clk 50–125 MHz Avalon-MM interface for Hard IP dynamic reconfi‐
guration interface which you can use to change the
value of read-only configuration registers at
run-time. This interface is optional. It is not
required for Arria 10 devices.
7-8 Clock Summary
UG-01097_avst
2014.12.15
Altera Corporation Reset and Clocks
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