Altera Stratix V Avalon-ST - Manual (Page 274)

Table 18-2: Link Hangs in L0
Possible Causes Symptoms and Root Causes Workarounds and Solutions
Avalon-ST signaling
violates Avalon-ST
protocol
Avalon-ST protocol violations
include the following errors:
• More than one
tx_st_sop
per
tx_st_eop
.
• Two or more
tx_st_eop’s
without a corresponding
tx_
st_sop.
•
rx_st_valid
is not asserted
with
tx_st_sop
or
tx_st_
eop
.
These errors are applicable to
both simulation and hardware.
Add logic to detect situations where
tx_st_
ready
remains deasserted for more than 100
cycles. Set post-triggering conditions to check
for the Avalon-ST signalling of last two TLPs to
verify correct
tx_st_sop
and
tx_st_eop
signalling.
Incorrect payload
size
Determine if the length field of
the last TLP transmitted by End
Point is greater than the InitFC
credit advertised by the link
partner. For simulation, refer to
the log file and simulation
dump. For hardware, use a
third-party logic analyzer trace
to capture PCIe transactions.
If the payload is greater than the initFC credit
advertised, you must either increase the InitFC
of the posted request to be greater than the max
payload size or reduce the payload size of the
requested TLP to be less than the InitFC value.
Flow control credit
overflows
Determine if the credit field
associated with the current TLP
type in the
tx_cred
bus is less
than the requested credit value.
When insufficient credits are
available, the core waits for the
link partner to release the
correct credit type. Sufficient
credits may be unavailable if the
link partner increments credits
more than expected, creating a
situation where the Stratix V
Hard IP for PCI Express IP Core
credit calculation is out-of-sink
with its link partner.
Add logic to detect conditions where the
tx_st_
ready
signal remains deasserted for more than
100 cycles. Set post-triggering conditions to
check the value of the
tx_cred*
and
tx_st_*
interfaces. Add a FIFO status signal to
determine if the TXFIFO is full.
UG-01097_avst
2014.12.15
Debugging Link Failure in L0 Due To Deassertion of tx_st_ready 18-5
Debugging Altera Corporation
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