Altera Stratix V Avalon-ST - Manual (Page 69)

Tradeoffs to Consider when Enabling Multiple Packets per Cycle
If you enable Multiple Packets Per Cycle under the Systems Settings heading, a TLP can start on a
128-bit boundary. This mode supports multiple start of packet and end of packet signals in a single cycle
when the Avalon-ST interface is 256 bits wide. It reduces the wasted bandwidth for small packets.
A comparison of the largest and smallest packet sizes illustrates this point. Large packets using the full
256 bits achieve the following throughput:
256/256*8 = 8 GBytes/sec
The smallest PCIe packet, such as a 3-dword memory read, uses 96 bits of the 256-bits bus and achieve the
following throughput:
96/256*8 = 3 GBytes/sec
If you enable mMultiple Packets Per Cycle, when a TLP ends in the upper 128 bits of the Avalon-ST bus,
a new TLP can start in the lower 128 bits Consequently, the bandwidth of small packets doubles:
96*2/256*8 = 3 GBytes/sec
This mode adds complexity to the Application Layer user decode logic. However, it could result in higher
throughput.
Figure 5-18: 256-Bit Avalon-ST RX Interface with Multiple Packets Per Cycle
The following figure illustrates this mode for a 256-bit Avalon-ST RX interface. In this figure
rx_st_eop[0]
and
rx_st_sop[1]
are asserted in the same cycle.
UG-01097_avst
2014.12.15
Tradeoffs to Consider when Enabling Multiple Packets per Cycle 5-17
Interfaces and Signal Descriptions Altera Corporation
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