Altera Stratix V Avalon-ST - Manual (Page 171)

Clocks and Reset
The PCI Express Base Specification requires an input reference clock, which is called
refclk
in this design.
The PCI Express Base Specification stipulates that the frequency of this clock be 100 MHz.
The PCI Express Base Specification also requires a system configuration time of 100 ms. To meet this
specification, IP core includes an embedded hard reset controller. This reset controller exits the reset state
after the I/O ring of the device is initialized.
Related Information
• Clock Signals on page 5-33
• Reset, Status, and Link Training Signals on page 5-34
Local Management Interface (LMI Interface)
The LMI bus provides access to the PCI Express Configuration Space in the Transaction Layer.
Related Information
LMI Signals on page 5-51
Hard IP Reconfiguration
The PCI Express reconfiguration bus allows you to dynamically change the
read-only
values stored in
the Configuration Registers.
Related Information
Hard IP Reconfiguration Interface on page 5-61
Transceiver Reconfiguration
The transceiver reconfiguration interface allows you to dynamically reconfigure the values of analog
settings in the PMA block of the transceiver. Dynamic reconfiguration is necessary to compensate for
process variations.
Related Information
Transceiver PHY IP Reconfiguration on page 16-1
Interrupts
The Hard IP for PCI Express offers the following interrupt mechanisms:
• Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge
handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configu‐
ration Space and is programmable using Configuration Space accesses.
• MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. In
contrast to the MSI capability structure, which contains all of the control and status information for
the interrupt vectors, the MSI-X Capability structure points to an MSI-X table structure and MSI-X
PBA structure which are stored in memory.
• Legacy interrupts—The
app_int_sts
port controls legacy interrupt generation. When
app_int_sts
is
asserted, the Hard IP generates an Assert_INT<n> message TLP.
10-4 Clocks and Reset
UG-01097_avst
2014.08.18
Altera Corporation IP Core Architecture
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