Altera Stratix V Avalon-ST - Manual (Page 276)

• Avalon Interface Specifications
• PCI Express Base Specification 2.1 or 3.0
• Design Debugging Using the SignalTap II Embedded Logic Analyzer
Setting Up Simulation
Changing the simulation parameters reduces simulation time and provides greater visibility.
Changing Between Serial and PIPE Simulation
By default, the Altera testbench runs a serial simulation. You can change between serial and PIPE
simulation by editing the top-level testbench file.
The
hip_ctrl_simu_mode_pipe
signal and
enable_pipe32_sim_hwtcl
parameter, specify serial or PIPE
simulation. When both are set to 1'b0, the simulation runs in serial mode. When both are set to 1'b1, the
simulation runs in PIPE mode. Complete the following steps to enable PIPE simulation. These steps
assume that the actual testbench is Gen3 x8 with an Avalon-ST 256-bit interface.:
1. In the top-level testbench, which is
<working_dir>/<variant>/testbench/<variant>_tb/simulation/<variant>_
tb.v , change the signal,
hip_ctrl_simu_mode_pipe
to 1'b1 as shown:
pcie_de_gen3_x8_ast256 pcie_de_gen3_x8_ast256_inst (.hip_ctrl_simu_mode_pipe
( 1'b1 ),
2. In the top-level HDL module for the Hard IP which is
<working_dir>/<variant>/testbench/<variant>_tb/
simulation/submodules/<variant>.v
change the parameter
enable_pipe32_sim_hwtcl
parameter to 1'b1
as shown:
altpcie_<dev>_hip_ast_hwtcl #( .enable_pipe32_sim_hwtcl ( 1 ),
Using the PIPE Interface for Gen1 and Gen2 Variants
Running the simulation in PIPE mode reduces simulation time and provides greater visibility.
Complete the following steps to simulate using the PIPE interface:
1. Change to your simulation directory,
<work_dir>/<variant>/testbench/<variant>_tb/simulation
2. Open
<variant>_tb.v .
3. Search for the string,
serial_sim_hwtcl
. Set the value of this parameter to 0 if it is 1.
4. Save
<variant>_tb.v .
Reducing Counter Values for Serial Simulations
You can accelerate simulation by reducing the value of counters whose default values are set for hardware,
not simulation.
Complete the following steps to reduce counter values for simulation:
1. Open
<work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/altpcie_tbed_<dev>_hwtcl.v .
2. Search for the string,
test_in
.
3. To reduce the value of several counters, set
test_in[0] = 1
.
4. Save altpcietb_bfm_top_rp.v .
UG-01097_avst
2014.12.15
Setting Up Simulation 18-7
Debugging Altera Corporation
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