Altera Stratix V Avalon-ST - Manual (Page 288)

Date Version Changes Made
• Added link to a Knowledge Base Solution that shows how to
observe the
test_in
bus for debugging.
• Removed optional 125 MHz reference clock frequency. This
option has not been tested extensively in hardware.
• Corrected channel placement diagrams for Gen3 x2 and Gen3 x4.
The CMU PLL should be shown in the Channel 4 location. For
Gen3 x2, the second data channel is Ch1. For Gen3 x4, the data
channels are Ch0 - Ch3.
• Corrected figure showing physical placement of PCIe Hard IP
modules for Arria V GZ devices.
• Added definition for
test_in[6]
and link to Knowledge Base
Solution on observing the PIPE interface signals on the
test_out
bus.
• Removed references to Gen2 x1 62.5 MHz configuration. This
configuration is not supported.
• Removed statement that Gen1 and Gen2 designs do not require
transceiver reconfiguration. Gen1 and Gen2 designs may require
transceiver reconfiguration to improve signal quality.
• Removed
reconfig_busy
port from connect between PHY IP
Core for PCI Express and the Transceiver Reconfiguration
Controller in the Altera Transceiver Reconfiguration Controller
Connectivity figure. The Transceiver Reconfiguration Controller
drives
reconfig_busy
port to the Altera PCIe Reconfig Driver.
• Removed soft reset controller .sdc constraints from the <install_dir>
/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altpcied_<dev>.sdc
example. These constraints are now in a separate file in the
synthesis/submodules directory.
• Updated Power Supply Voltage Requirements table.
• For Arria V GZ and Stratix V devices, corrected channel
placement diagrams for x8. Both Gen3 Channel Placement Using
the CMU and ATX PLLs and Gen1 and Gen2 Channel Placement
Using the ATX PLL show the ATX PLL1 in bank 1 being used.
However, ATX PLL 1 in bank 0 is actually used.
UG-01097_avst
2014.12.15
Revision History for the Avalon-St Interface C-3
Additional Information Altera Corporation
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