Configuration space bypass mode – Altera Stratix V Avalon-ST User Manual
Page 174
The Configuration Space also generates all messages (PME#, INT, error, slot power limit), MSI requests,
and completion packets from configuration requests that flow in the direction of the root complex, except
slot power limit messages, which are generated by a downstream port. All such transactions are
dependent upon the content of the PCI Express Configuration Space as described in the PCI Express Base
Specification.
Related Information
•
Type 0 Configuration Space Registers
•
Type 1 Configuration Space Registers
•
Configuration Space Bypass Mode
When you select Enable Configuration Space Bypass under the System Settings heading of the
parameter editor, the Stratix V Hard IP for PCI Express bypasses the Transaction Layer Configuration
Space registers included as part of the hard IP, allowing you to substitute a custom Configuration Space
implemented in soft logic. If you implement Configuration Space Bypass mode, the Configuration
Shadow Extension Bus is not available. In Configuration Space Bypass mode, all received Type 0 configu‐
ration writes and reads are forwarded to the Avalon-ST interface.
In Configuration Space Bypass mode, you must also implement all of the TLP BAR matching and
completion tag checking in soft logic.
If you enable Configuration Space Bypass mode, you can implement the following features in soft logic:
• Resizable BARs
• Latency Tolerance Reporting
• Multicast
• Dynamic Power Allocation
• Alternative Routing-ID Interpretation (ARI)
• Single Root I/O Virtualization (SR-IOV)
• Multi-functions
The RX Buffer, Flow Control, DL and PHY layers from the Stratix V Hard IP for PCI Express are retained
in the Hard IP.
UG-01097_avst
2014.08.18
Configuration Space Bypass Mode
10-7
IP Core Architecture
Altera Corporation