Motorola DSP96002 - Manual (Page 137)

MOTOROLA DSP96002 USER’S MANUAL 7 - 51
able memory would typically load the Offset register with +4 to perform 32-bit aligned accesses. DMA trans-
fers to/from I/O peripherals would load the Offset register with zero to continuously access the same ad-
dress.
7.5.9 DMA Addressing Modes
The DMA Controller may be programmed for address calculation and updates in the same manner as the
registers in the Address Generation Unit. The DMA Modifier registers are completely identical to the Modifier
registers M0-M7. In this way, the DMA source and/or destination address registers may be updated using
linear, bit-reverse or modulo address calculations. See Section 5.8 for a description of how to program the
Modifier registers.
7.5.10 DMA Restrictions
The following are some restrictions that apply to the DMA operation:
1. Source/Destination address area must be wholly internal or external. The DMA cannot handle
blocks of data that are partially internal and partially external. These blocks must be handled as
two separate blocks, one internal and the other external.
If the Source/Destination address area is defined as internal, and an address that is greater than
the highest internal address is generated by the DMA ALU, the address will wrap around into
the internal address space.
If the Source/Destination address area is defined as external, and an address that is less than
the lowest external address is generated by the DMA ALU, the address will access external
memory anyway. Note that X and Y Data Memory locations that are always considered as in-
ternal by the core may be accessed as external memory locations by the DMA.
2. WAIT and STOP will halt DMA transfers. STOP and WAIT may disable the internal clock in the
middle of a DMA transfer. The user should stop DMA transfers before executing the STOP or
WAIT instructions. To stop DMA transfers, DE must be cleared. Before executing the STOP or
WAIT instruction, the user should poll the DTD bit (or receive a DMA interrupt when DTD is set)
to ensure that the present DMA transfer has been completed.
Note that the use of these instructions already require some kind of software management in
multiprocessing systems, since there is no way that the external devices could know that the
chip entered the STOP or WAIT state.
3. Only the Host Transmit/Receive Data registers may be accessed by the DMA Controller when
specifying source or destination in the internal I/O space.
4. During any (internal or external) read-modify-write core access, the DMA is not permitted to
complete or initiate any DMA transfer. The DMA is halted as if it is trying to access an external
bus and it is not the bus master.
5. Cases where DMA operation is affected:
1. If the core is accessing external memory thorough both ports simultaneously, and one or
both of the core accesses are delayed due to memory wait, internal DMA transfers will be
delayed because the chip clock is generating wait states, freezing internal activity.
2. If the core is doing one external access and the DMA is also doing an external access
thorough the other port, and the DMA access is delayed (for example, due to wait states),
the access by the core in the other port is not affected. The DMA has a separate wait
mechanism, and in this case the core continues normal execution since the core clock
does not enter wait states.