Motorola DSP96002 - Manual (Page 177)

MOTOROLA DSP96002 USER’S MANUAL 10 - 11
software developer debug sections of code which do not have a normal flow or are getting hung up in infinite
loops. The trace counter also enables the user to debug areas of code which are time critical.
To enable the trace mode of operation the counter is loaded with a value, the program counter is set to the
start location of the instruction(s) to be executed real-time, the trace mode is selected in the OSCR and the
DSP96002 exits the debug mode by executing the appropriate command issued by the external command
controller.
Upon exiting the debug mode the counter is decremented after each execution of an instruction. Interrupts
are serviceable and all instructions executed (including fast interrupt services) will decrement the trace
counter. Upon decrementing to zero, the DSP96002 will re-enter the debug mode (interrupt service break-
point signal, ISBKPT, set), the trace occurrence bit in the OSCR will be set and the DSO pin will be toggled
to indicate that the DSP96002 has entered debug mode and is requesting service.
The Trace Counter is cleared by hardware reset or whenever the debug mode of operation is entered. Fig-
ure 10-6 illustrates a block diagram of the Trace Counter logic.
10.6 OnCE

SERIAL PORT TIMING
External data is fed into the serial input line by clocking each bit at a variable rate. The minimum clock rate
should be 1 MHZ and the maximum clock rate should be 10 MHZ. The serial input bit must be stable at least
10 ns before the falling edge of the serial clock (set up time) and must remain stable for at least 10 ns after
the falling edge of the clock (hold time).
The serial output line will clock out data from selected register as specified by the last command entered
from the command controller. The data bit value will be valid on the rising edge of the clock and will remain
valid for at least 10 ns after the rising edge of the clock.
After entering the debug mode of operation the serial output line will go low for at least one T cycle to flag
the command controller that the DSP96002 is requesting a breakpoint or trace service.
10.7 METHODS OF ENTERING THE DEBUG MODE
Entering the Debug Mode is acknowledged by the chip by toggling the DSO line for 1 T cycle. This informs
the external command controller that the chip has entered the Debug Mode and is waiting for commands.
There are seven ways in which the Debug Mode may be entered.
10.7.1 External request during
—
R
—
E
—
S
—
E
–
T
Holding the
—
D
–
R line asserted during the assertion of
—
R
—
E
—
S
—
E
–
T causes the chip to enter the De-
bug Mode. After receiving the acknowledge, the command controller must deassert the
—
D
–
R line. Note
that in this case the chip does not perform any fetch or memory access before entering the Debug Mode.
10.7.2 External request during normal activity
Holding the
—
D
–
R line asserted during normal chip activity causes the chip to finish the execution of the
current instruction and then enter the Debug Mode. After receiving the acknowledge, the command control-
ler must deassert the
—
D
–
R line. Note that in this case the chip completes the execution of the current in-
struction and stops after the newly fetched instruction enters the instruction latch. This process is the same