Motorola DSP96002 - Manual (Page 48)

MOTOROLA DSP96002 USER’S MANUAL 4 - 9
The Data ALU performs rounding of the result to the precision specified by the instruction. The DSP96002
supports only single extended and single precision results. The DSP96002 implements all four rounding
modes specified by the IEEE standard. These modes are round to nearest (RN), round toward zero (RZ),
round toward plus infinity (RP) and round toward minus infinity (RM). The rounding definitions are listed be-
low.
RN Round to Nearest Even (default) - In this mode the representable value nearest to the infinitely pre-
cise value will be delivered as result. If the two nearest values are equally near, the one with the least
significand bit equal to zero (even) will be the result – e. g., 1.65 rounds to 1.6 whereas 1.75 rounds
to 1.8.
RZ Round Toward Zero - In this mode the result will be the value closest to, and no greater in magnitude
than the infinitely precise result. This mode is sometimes called "truncation mode" or "chopped
mode" since the bits to the right of the rounding point are discarded – e. g., 1.65 rounds to 1.6 and -
1.65 rounds to -1.6.
RM Round Toward Minus Infinity - In this mode the result will be the value closest to, and no greater than
the infinitely precise result (possibly minus infinity) – e. g., 1.65 rounds to 1.6 and -1.65 rounds
to -1.7.
RP Round Toward Plus Infinity - In this mode the result will be the value closest to, and no less than the
infinitely precise result (possibly plus infinity) – e. g., 1.65 rounds to 1.7 and -1.65 rounds to -1.6.
4.7.23 Reserved Status (Bits 23,24,25)
These bits are reserved for future expansion and will read as zero during read operations. They should be
written with zero for future compatibility.
4.7.24 MR Multiply Precision Control (MP) Bit 26
The multiply precision control bit specifies the output precision of the multiply operation in the FMPY//FADD,
FMPY//FADDSUB and FMPY//FSUB instructions. If MP is cleared, then the output precision of the multiply
operation is determined by the accompanying instruction (FADD, FADDSUB or FSUB). If MP is set, then
the output precision of the multiply operation is the maximum precision supported by the hardware (single
extended precision in theDSP96002). MP is cleared during processor reset.
For example, if MP=0 and the accompanying instruction is FADD.S, then the multiply output precision will
be single precision. If MP=1 and the accompanying instruction is FADD.S, then the multiply output precision
will be single extended precision. If the accompanying instruction is FADD.X, then the multiply output pre-
cision will be single extended precision independently of the state of MP.
MP Multiply Precision Control
0
Output Precision Determined By The Accompanying Instruction
1 Maximum Output Precision (SEP in theDSP96002)
4.7.25 Flush to Zero (FZ) Bit 27
The Flush to Zero bit specifies one of two modes for handling floating-point underflow - the IEEE gradual
underflow mode using denormalized numbers and the Flush to Zero mode. If FZ is cleared, floating-point
underflows are processed in full conformance to the IEEE 754-1985 floating-point standard, resulting in the
possible generation of denormalized numbers. If a Data ALU source operand or result is a denormalized
number, the IEEE underflow mode may insert additional instruction cycles for normalization and denormal-