Motorola DSP96002 - Manual (Page 26)

MOTOROLA DSP96002 USER’S MANUAL 3 - 3
3.2.3 Data ALU
The Data ALU performs all of the arithmetic and logical operations on data operands. The Data ALU con-
sists of ten 96-bit general purpose registers, a 32-bit barrel shifter, a 32-bit adder, and a 32-bit parallel mul-
tiplier. Data ALU registers may be read or written over the XDB and YDB as 32 or 64-bit operands. The
Data ALU is capable of multiplication, addition, subtraction, format conversion, shifting and logical opera-
tions in one instruction cycle. Data ALU source operands may be 32 or 96-bits and originate from the gen-
eral purpose register file. Data ALU results are always stored in one of the general purpose registers. Float-
ing-point Data ALU operations always have a 96-bit result. Integer (fixed-point) Data ALU operations have
a 32 or 64-bit result.
The Data ALU fully implements the IEEE Standard 754 for binary floating-point arithmetic. The operations
are supported in three data formats: 32-bit two’s-complement fixed-point, 32-bit unsigned-magnitude fixed-
point and 44-bit IEEE single extended precision floating-point. All the floating-point computations are per-
formed using the single extended precision format and the results are automatically rounded to single pre-
cision or single extended precision numbers as programmed. All four IEEE rounding modes (round to zero,
round to nearest, round to plus infinity and round to minus infinity) are supported for all floating-point oper-
ations and conversions. The IEEE gradual underflow with denormalized numbers is supported by the IEEE
mode. In the IEEE mode, if input operand(s) or output result(s) are denormalized numbers, additional in-
struction cycles are required to process these numbers per the IEEE standard. A "Flush to Zero" mode is
also provided which forces all floating point result underflows to zero (all denormalized input operands are
considered as being zero). The Flush to Zero mode never requires any additional instruction cycles.
Refer to Section 3.3 for a detailed description of the Data ALU architecture.
3.2.4 AGU
The AGU performs all of the address storage and effective address calculations necessary to address data
operands in memory and it is used by both the core and the on-chip DMA Controller. The AGU operates in
parallel with other chip resources to minimize address generation overhead. The AGU contains eight Ad-
dress Registers (R0-R7), eight Offset Registers (N0-N7), and eight Modifier Registers (M0-M7). The Ad-
dress Registers are 32-bit registers which may contain any address or data. Each Address Register may
be accessed for output to the XAB, YAB, and PAB. The modifier and offset registers are 32-bit registers
which are normally used to control updating of the address registers.
AGU registers may be read or written over the Global Data Bus as 32-bit operands. The AGU can generate
two 32-bit addresses every instruction cycle - one for any two of the XAB, YAB or PAB. The AGU can di-
rectly address 4,294,967,296 locations on the XAB and 4,294,967,296 locations on the YAB - a total capa-
bility of 8,589,934,592 32-bit data words. Refer to Section 3.4 for a detailed description of the AGU archi-
tecture.
3.2.5 X Data Memory
The X Data Memory may contain both data RAM and ROM. The X Data RAM is a 32-bit wide internal mem-
ory and occupies the lowest 512 locations in X Memory Space. The X Data ROM is also a 32-bit wide in-
ternal memory and occupies 1024 locations in X Memory Space. Addresses are received from the XAB
and data transfers occur on the XDB. The X memory is a dual-access memory in the sense that it may be
accessed twice during a cycle: once by the core and once by the DMA. X memory may be expanded off
chip.