Motorola DSP96002 - Manual (Page 42)

MOTOROLA DSP96002 USER’S MANUAL 4 - 3
floating point number a format conversion to/from the internal representation takes place. The format con-
version is performed automatically and is transparent to the user.
The registers serve as input pipeline registers between the XDB and YDB and the multiplier and/or adder.
They are used as Data ALU source and/or destination operands allowing also new operands to be loaded
for the next instruction while the register contents are used by the current instruction. They may also be read
back out to the appropriate data bus to implement memory delay operations and save/restore operations
for interrupt service routines.
4.2.1 Data ALU Auxiliary Registers (D8, D9)
D8 and D9 are two 96-bit data registers which are mainly present to permit a four instruction Radix-2 FFT
butterfly. Operations with these registers are limited. They may be source operands only in multiply opera-
tions and source or destination operands in MOVE instructions. These registers are useful for extra multi-
plier input registers, pipelining registers, holding constants for compilers and temporary storage.
4.2.2 Data ALU General Purpose Registers (D0-D7)
D0, D1, D2, D3, D4, D5, D6 and D7 are eight general purpose data registers in the sense that MOVE in-
structions and arithmetic operations do not differentiate between them. They are used as Data ALU source
and destination operands for most of the Data ALU instructions.
4.3 ADDRESS REGISTER FILES (R0-R3 AND R4-R7)
The eight address registers, R0-R7, are 32-bits wide and may contain addresses or general purpose data.
The 32-bit address in a selected address register is used in the calculation of the effective address of an
operand. This address may point to data directly or may be modified by a register offset. Most addressing
modes modify the selected address register in a read-modify-write fashion. Typically, the address register
is accessed, used as input to its associated modulo arithmetic unit, modified by the arithmetic unit and writ-
ten back into the selected register. The form of address register modification performed by the modulo arith-
metic unit is controlled by the contents of the offset and modifier registers discussed below. The contents
of an address register may be transferred to/from an effective address held in a temporary address register.
4.4 OFFSET REGISTER FILES (N0-N3 AND N4-N7)
The eight offset registers, N0-N7, are 32-bits wide and may contain offset values used to increment and
decrement address registers in address register update calculations or they may be used for general pur-
pose storage. In addition, the contents of an offset register may be used to step through a table at some
rate for waveform generation or may specify the offset into a table or the base of the table. An offset register
will be accessed for an address register update calculation involving an address register of the same num-
ber (i.e., N0 is accessed when R0 is to be updated, N1 for R1, etc.).
4.5 MODIFIER REGISTER FILES (M0-M3 AND M4-M7)
The eight modifier registers, M0-M7, are 32-bits wide and may contain values which specify address arith-
metic types used in address register update calculations (i.e., linear, reverse carry, and modulo) or they may
be used for general purpose storage. When specifying modulo arithmetic, a modifier register will also spec-
ify the modulo value to be used. Refer to Section 5.8 for a description of the modifier types. A modifier reg-