Motorola DSP96002 - Manual (Page 799)

MOTOROLA 17
Notice that the code doesn’t fall within the critical sectors, but rather in the initialization
code.
PLOCK is the first instruction fetched in cache mode.
4. Now the cache is ready for normal operation with 2 sectors locked and 6 sectors in un-
locked mode. Notice that a fetch from one of the locked sectors (addresses 0 to 200)
will not cause a miss since the code for these sectors was brought into the cache while
in the processor is in PRAM mode.
5. The user can lock an additional sector dynamically. The sequence is similar to the one
shown in steps 2 and 3, but a dynamically locked cache sector will not necessarily con-
tain the valid data and would therefore be filled by word misses each time a new word
is fetched.
6. It would be wise to place time critical routines on sector boundaries. This would give
optimal cache sector utilization. The compiler could certainly obey this constraint.
7. To unlock the cache sector containing addresses 128 to 255, for example, all the user
has to do is:
MOVE #140, R0 ; load effective address to r0
NOP ; pipeline delay
PUNLOCK R0 ; unlock sector containing address 128
Notice that address 140 was used as an example since it belongs to the range 128 to 255.
8. To unlock all the locked cache sectors the code should be:
PFREE
This instruction is useful in case the user forgets which sectors or addresses were previ-
ously locked, or as a software reset to the locking mechanism.
9. When debugging the software or the system, the user can enter the debug mode at any
time and observe the tags, the valid-bits, the lock bits, and the least recently used sec-
tor to be replaced next.
10. To execute the bootstrap program the user switches to PRAM mode, executes the 3
NOPs needed for pipeline delay, performs a PFLUSH, and only then switches to boot-
strap mode: