Motorola DSP96002 - Manual (Page 67)

5 - 14 DSP96002 USER’S MANUAL MOTOROLA
5.7 ADDRESSING MODES
The DSP96002 instruction set contains a full set of operand addressing modes. All address calculations
are performed in the Address Generation Unit to minimize execution time and loop overhead.
Addressing modes specify whether the operand(s) is in a register or memory and provide the specific ad-
dress of the operand(s). An effective address in an instruction will specify an addressing mode, and for
some addressing modes the effective address will further specify an address register. In addition, address
register indirect modes require additional address modifier information which is not encoded in the instruc-
tion. The address modifier information is specified in the selected address modifier register(s). All memory
references require one address modifier and the XY memory reference requires one or two address mod-
ifiers. The definition of certain instructions implies the use of specific registers and the addressing modes
used.
Address register indirect modes require an offset and a modifier register for use in address calculations.
These registers are implied by the address register specified in an effective address in the instruction word.
Each offset register Nn and each modifier register Mn is assigned to an address register Rn having the
same register number n. Thus the assigned registers are M0;N0;R0, M1;N1;R1, M2;N2;R2, M3;N3;R3,
M4;N4;R4, M5;N5;R5, M6;N6;R6 and M7;N7;R7. The address register Rn is used as the address register,
the offset register Nn is used to specify an optional offset and the modifier register Mn is used to specify an
addressing mode modifier.
The addressing modes are grouped into three categories: register direct, address register indirect and spe-
cial. These addressing modes are described below. Refer to Figure 5-7 for a summary of the addressing
modes and operand references.
5.7.1 Register Direct Modes
These effective addressing modes specify that the operand is in one (or more) of the 30 Data ALU registers,
10 floating-point registers, 24 address registers or 7 control registers.
5.7.1.1 Data or Control Register Direct
The operand is in one, two or three Data ALU register(s) as specified in a portion of the data bus movement
field in the instruction. This addressing mode is also used to specify a control register operand for special
instructions. This reference is classified as a register reference.
5.7.1.2 Address Register Direct
The operand is in one of the 24 address registers specified by an effective address in the instruction. This
reference is classified as a register reference.
CAUTION:
Due to pipelining, if an address register (Mn, Nn, or Rn) is changed with a MOVE
instruction, the new contents will not be available for use as a pointer until the second
following instruction.