Motorola DSP96002 - Manual (Page 31)

3 - 8 DSP96002 USER’S MANUAL MOTOROLA
For the floating-point multiplication the Multiplier accepts two 44-bit input operands, and outputs one 44-bit
result. The operation of the floating-point Multiplier occurs independently and in parallel with the operation
of the floating-point Adder and with the XDB and YDB activity. For the fixed-point multiplication the Multi-
plier accepts two 32-bit input operands, and outputs one 64-bit result. The operation of the fixed point Mul-
tiplier occurs independently and in parallel with the XDB and YDB activity. The Data ALU registers can be
used by the programmer to implement Data ALU pipelines.
The Multiplier is implemented in asynchronous logic and all multiplication operations occur in one instruc-
tion cycle. Latches are provided on the Multiplier input operand buses to avoid race conditions. The major
components of the Multiply Unit are listed below.
• Multiplier Array
• Multiplier Control Recoder
• Exponent Adder
3.3.1.1 Multiplier Array
The multiplier array is a 32 X 32-bit asynchronous, parallel multiplier with 64-bit result. The multiplier array
is based on the modified Booth’s algorithm. The array performs signed/unsigned fixed-point multiplications
with an integer data representation and floating-point multiplications using a 32-bit mantissa. The multiplier
array performs automatic rounding to 32-bit result mantissa for the floating-point multiplications according
to the IEEE Standard 754 for single extended precision. If rounding to IEEE single precision is specified
(explicitly by the instruction or implicitly by the MR register), the result is rounded to 24-bit mantissa accord-
ing to IEEE Standard 754 for single precision. The four IEEE rounding modes are supported; the rounding
mode is specified by the rounding mode bits R1, R0 in the IER register.
3.3.1.2 Multiplier Control Recoder
The multiplier control decoder directs the operation of the Multiplier array and performs multiplier operand
recoding for the modified Booth’s algorithm multiplication.
3.3.1.3 Exponent Adder
The Exponent Adder is an 11-bit adder which serves as an adder for the exponents of the two operands of
the multiplication. It actually computes the sum between the two input exponents and subtracts the bias.
The resultant exponent is stored in the high portion of the destination register.
3.3.2 Adder Unit
The Adder is the second arithmetic processing unit of the Data ALU and performs all signed/unsigned in-
teger fixed-point add, subtract and shift operations on the data operands as well as floating-point add, sub-
tract and add-subtract. The floating-point add-subtract operation consists of a simultaneous add and sub-
tract performed on the same input operands. This operation is useful for implementing FFT’s (any Radix or
type) and other transforms.
The operation of the floating-point Adder/Subtracter occurs independently and in parallel with the operation
of the floating-point Multiplier and with the XDB and YDB activity.
The operation of the fixed-point Adder occurs independently and in parallel with the XDB and YDB activity.
The Data ALU registers provide pipelining for both Data ALU Adder inputs and outputs.