Motorola DSP96002 - Manual (Page 649)

B-130 DSP96002 USER’S MANUAL MOTOROLA
fmpy d4,d8,d3 fadd.s d3,d1 x:(r0)+,d4.s d5.s,d2.s 1 1
fmpy d4,d0,d3 fadd.s d3,d2 x:(r0)+,d4.s d1.s,y:(r5)+n5 1 1
fmpy d4,d6,d3 fadd.s d3,d2 x:(r0)+,d4.s 1 1
fmpy d4,d7,d3 fadd.s d3,d2 x:(r0)+,d4.s 1 1
fmpy d4,d8,d3 fadd.s d3,d2 x:(r0)+,d4.s d5.s,d1.s 1 1
fmpy d4,d0,d3 fadd.s d3,d1 x:(r0)+,d4.s d2.s,y:(r5)+n5 1 1
fmpy d4,d6,d3 fadd.s d3,d1 x:(r0)+,d4.s 1 1
fmpy d4,d7,d3 fadd.s d3,d1 x:(r0)+,d4.s 1 1
fmpy d4,d8,d3 fadd.s d3,d1 x:(r0)+,d4.s d5.s,d2.s 1 1
fmpy d4,d0,d3 fadd.s d3,d2 x:(r0)+,d4.s d1.s,y:(r5)+n5 1 1
fmpy d4,d6,d3 fadd.s d3,d2 x:(r0)+,d4.s d5.s,d1.s 1 1
fmpy d4,d7,d3 fadd.s d3,d2 x:(r0)+,d4.s y:(r4)+,d0.s
;junk into d0.s 1 1
fadd.s d3,d2 y:(r4)+n4,d8.s 1 1
move d2.s,y:(r5)+n5 1 1
endall --- ---
Totals: 30 87
B.1.56 [8x8] by [8x8] Matrix Multiplication (Modulo-Aligned)
;This routine performs an [8x8] by [8x8] matrix multiplication
;for the 96000 floating-point DSP chip. Sample data is given
;for N=8. The data for all matrices is stored in row major
;format. For example, take the matrix A:
;
; A(1,1) ... A(1,N)
; . . .
; . . .
; A(N,1) ... A(N,N)
;
;Matrix A’s elements are stored as such:
;amatrix dc A(1,1),A(1,2),...,A(1,N),A(2,1),A(2,2),...,A(2,N), ...
;
;Matrix A is in X memory, while matrices B and C are in Y memory.
;Since modulo N**2 addressing is used for all matrices, the first
;k least significant bits of the address of the beginning of any
;matrix storage area must be equal to zero, where 2**k >= N**2.
;
;This routine takes 15 + 8*74 = 607 instruction cycles.
;
;
;
Program ICycles