Motorola DSP96002 - Manual (Page 95)

MOTOROLA DSP96002 USER’S MANUAL 7 - 9
machine is responsible for ensuring that
—
R
—
A
–
S or
—
C
—
A
–
S timeouts do not occur. Since typical
—
R
—
A
–
S and
—
C
—
A
–
S timeouts are 10-100
µ
sec, one of the simplest solutions is to perform a hardware refresh
which deasserts both
—
R
—
A
–
S and
—
C
—
A
–
S. If refresh is performed often enough,
—
R
—
A
–
S and
—
C
—
A
–
S timeout will never happen.
The serial port of VRAM devices is clocked by a serial clock SC. Since the serial shift register is dynamic,
there is a minimum frequency at which the shift register must be clocked to refresh its contents. This fre-
quency is typically about 20 kHz (50
µ
sec refresh period). The DSP96002 does not provide any internal sup-
port for SC timeouts. The external state machine is responsible for ensuring that SC timeouts do not occur.
If an SC timeout does occur, the external state machine cancels (ignores) the effect of the
—
T
–
T signal in
the next external bus cycle to force a reload of the serial shift register. Fortunately, future 1Mbit VRAMs are
being specified with static shift registers so the SC timeout problem should go away.
7.2.2.4 DMA Accesses
External DMA accesses to P, X or Y memory spaces are normal bus cycles and cannot be distinguished
from CPU read/write cycles. Therefore DMA accesses can use the
—
T
–
T pin and do not need any special
treatment by external hardware.
7.2.2.5 Multiple Memory Banks
Multiple memory banks exist when there are more external memories than needed just to cover the 32-bit
data bus size. In this case, the external memory controller typically selects between banks by enabling one
of several row address strobe (
—
R
—
A
–
S) signals or column address strobe (
—
C
—
A
–
S) signals based on
several address lines. Since changes from one memory bank to another will cause a page fault, multiple
memory banks are allowed and no special treatment is required.
7.2.2.6 Multiple Memory Controllers
Multiple memory controllers may exist to support fast access modes with multiple external physical memo-
ries. Since the page circuit can monitor multiple memory spaces and detect or ignore changes in memory
spaces, multiple memory controllers are allowed and no special treatment is required.
7.3 EXPANSION PORTS SELECTION
Every memory space (X, Y and P) is divided into 8 equal portions. The division is fixed, that is, the sizes of
the portions are fixed at 0.5 gigawords per portion and the address boundaries are fixed. Each portion of
each memory space may be individually assigned to one of the external expansion ports (Port A or B). The
mapping is controlled by the Port Select Register (PSR).
7.3.1 Port Select Register (PSR)
The Port Select Register is a 32-bit wide read/write register situated in the X I/O memory space. For each
portion of each memory space there is a bit in the Port Select Register (PSR): if the bit is cleared, the re-
spective portion goes thorough Port A, and if the bit is set, then it goes thorough Port B. Any memory seg-