Motorola DSP96002 - Manual (Page 786)

4 MOTOROLA
The DSP96002 instruction cache is a “real-time” cache and therefore it has no inherent
penalty on a cache miss. In other words, if there is a cache hit, it takes exactly one bus
cycle to fetch the instruction from the on-chip cache - like fetching any other data from an
on-chip memory. If there is a cache miss, it behaves exactly as a “normal” instruction fetch,
as if it were fetching any other data from that external memory.
Furthermore, a “real-time” instruction cache allows the user to declare some code areas
as time-critical and therefore “non-replaceable”. Six new instructions have been added to
the instruction set, allowing the user to lock sectors of the cache, and to flush the cache
contents under software control.
The following list is a summary of the instruction cache features:
• 1K, 32-bit wide, on-chip instruction cache
• Switching from PRAM mode to cache mode is software controlled
• Fully compatible with the DSP96002 PRAM mode when cache is disabled
• 8-way, fully associative, sectored cache
• One-word transfer granularity
• Least recently used (LRU) sector replacement algorithm
• User transparent - no user management required
• No additional wait states on cache miss
• Global cache mode, allowing normal cache operation
• Individual sector locking, preventing replacement of sector contents, but allowing
updating of new entries within sector
• Global cache flush in software, allowing immediate clearing of the contents of the
Instruction Cache
• Global PRAM mode, allowing compatibility with original architecture (including
PRAM disabled and DMA to/from program memory)
• Full cache observability (tags, valid-bits, LRU, locked sectors) with OnCE
commands in debug mode.
2.2 INSTRUCTION CACHE STRUCTURE
A cache controller has been added to the existing Internal Program RAM. Figure 2 shows
a block diagram of the instruction cache controller.
The internal program RAM contains 1024 32-bit words, logically divided into eight 128-
word cache sectors. In a similar way, the external program memory is virtually divided into
128-word sectors. The term “sector” is used, rather than “block”, since a sectored-cache
distinguishes between “sectors” which are the basic replacement units, and “blocks” which
are the basic transfer units. In our case a “block” is a 32 bit word so that one can use the
terms “block” and “word” interchangeably.