Motorola DSP96002 - Manual (Page 22)

MOTOROLA DSP96002 USER’S MANUAL 2 - 19
ZZ = ^end_of_sequence v ( ext_acc_req & ^
—
D
—
B
–
G ) (note 3)
ZW = ^ext_acc_req & ^
—
B
–
G
WX = ^ext_acc_req &
—
B
–
G
WY = NON-EXISTENT ARC (note 2)
WZ = ext_acc_req
WW = ^ext_acc_req & ^
—
B
–
G
Notes: 1. Illegal arcs in DSP96002 since once the request of the bus is pending, it will not be canceled
before the execution of the access.
2. Non-existent arc since if ext_acc_req arrives together with the negation of
—
B
–
G, the device
becomes active master and begins its bus transfers.
3.
—
D
—
B
–
G is
—
B
–
G delayed by one phase. This is done to provide a response to the
ext_acc_req signal when it is asserted at the same phase together with
—
B
–
G negation.
5.16.3 Bus Arbitration Example Cases
5.16.3.1 Case 1 – Normal
If the device requesting mastership asserts
—
B
–
R: the arbiter asserts the requesting devices’
—
B
–
G and
—
B
–
B is deasserted indicating the bus is not busy. The requesting device will assert
—
B
–
A.
5.16.3.2 Case 2 – Bus Busy
If the device requesting mastership asserts
—
B
–
R: the arbiter responds by asserting the requesting devic-
es’
—
B
–
G; however, the bus is busy because
—
B
–
B is asserted. The requesting device will not assert
—
B
–
A until
—
B
–
B is deasserted.
5.16.3.3 Case 3 – Low Priority
If the device requesting mastership asserts
—
B
–
R: the arbiter withholds asserting the requesting devices’
—
B
–
G because a higher priority device requested the bus.
—
B
–
A of the requesting device will not be as-
serted.
5.16.3.4 Case 4 – Default
If a device does not request the bus and it is not in the bus parking state but rather it is in the idle state: the
arbiter, by design (i. e., default), asserts
—
B
–
G.
—
B
–
A will remain deasserted.