Motorola DSP96002 - Manual (Page 45)

4 - 6 DSP96002 USER’S MANUAL MOTOROLA
4.7.2 CCR Overflow (V) Bit 1
The integer overflow bit is set if an arithmetic overflow occurred in a fixed point operation. This means that
the result is not representable in the destination size. The V bit is not affected by floating point operations
unless they have a fixed point result. The overflow bit is also modified by Address Generation Unit operation
when executing MOVETA instructions. The V bit is cleared during processor reset.
4.7.3 CCR Zero (Z) Bit 2
The zero bit is set if the result equals plus or minus zero in a floating point or zero in a fixed point operation.
The zero bit is also modified by Address Generation Unit operation when executing MOVETA instructions.
The Z bit is cleared during processor reset.
4.7.4 CCR Negative (N) Bit 3
The negative bit is set if the result is negative in a floating point or zero in a fixed point operation. The neg-
ative bit is also modified by Address Generation Unit operation when executing MOVETA instructions. The
N bit is cleared during processor reset.
4.7.5 CCR Infinity (I) Bit 4
The infinity bit is set if the result of a floating-point operation is infinity. The I bit is not affected by fixed point
operations. The I bit is cleared during processor reset.
4.7.6 CCR Local Reject (LR) Bit 5
The local reject bit is used for trivial reject testing of floating point or fixed point operands in graphics appli-
cations. The LR bit is cleared during processor reset.
4.7.7 CCR Reject (
–
R) Bit 6
The global reject bit is used for trivial reject testing of floating point or fixed point operands in graphics ap-
plications. The
–
R bit is cleared during processor reset.
4.7.8 CCR Accept (A) Bit 7
The accept bit is used for trivial accept testing of floating point or fixed point operands of floating point or
fixed point operands in graphics applications. The A bit is cleared during processor reset.
4.7.9 ER Inexact (INX) Bit 8
The inexact bit is set if a floating-point result is inexact. This occurs when the mantissa of the intermediate
result from the Data ALU operation is rounded to the specified precision. If the rounded mantissa transferred
to the Dn register differs from the unrounded intermediate result mantissa, a loss of accuracy has occurred
and the INX bit will be set. The INX bit is not affected by fixed point operations. The INX bit is cleared during
processor reset.