Motorola DSP96002 - Manual (Page 221)

MOTOROLA DSP96002 USER’S MANUAL A - 33
BCHG Bit Test and Change BCHG
Operation:
D{n}
→
C;
~D{n}
→
D{n}
D{n}
→
C;
~D{n}
→
D{n}
D{n}
→
C;
~D{n}
→
D{n}
D{n}
→
C;
~D{n}
→
D{n}
D{n}
→
C;
~D{n}
→
D{n}
D{n} →
C;
~D{n}
→
D{n}
D{n}
→
C;
~D{n}
→
D{n}
Assembler Syntax:
BCHG #bit,X: ea
BCHG #bit,X: aa
BCHG #bit,X: pp
BCHG #bit,Y: ea
BCHG #bit,Y: aa
BCHG #bit,Y: pp
BCHG #bit,D
Description:
The nth bit of the destination operand is tested and the state of the nth bit is reflected in the C condition
code bit. After the test, the state of the nth bit is changed in the destination. All memory alterable ad-
dressing modes may be used. Register, Absolute Short and I/O Short addressing may also be used.
The bit to be tested is selected by an immediate bit number 0-31. This instruction performs a read-modify-
write operation on the destination operand and requires two destination accesses. This instruction pro-
vides a test-and-change capability which is useful for synchronizing multiple processors using a shared
memory. See Section A.10 for restrictions.
CCR Condition Codes:
For destination operand SR:
C - Changed if bit 0 is specified. Not affected otherwise.
V - Changed if bit 1 is specified. Not affected otherwise.
Z - Changed if bit 2 is specified. Not affected otherwise.
N - Changed if bit 3 is specified. Not affected otherwise.
I - Changed if bit 4 is specified. Not affected otherwise.
LR - Changed if bit 5 is specified. Not affected otherwise.
–
R - Changed if bit 6 is specified. Not affected otherwise.
A - Changed if bit 7 is specified. Not affected otherwise.