Motorola DSP96002 - Manual (Page 807)

MOTOROLA 25
5.4.2 Displaying the Valid-bits of Specific Cache Locations Starting From
Address xxx
This routine uses R0 as pointer to cache addresses. Therefore this register has to be read
before the routine, and has to be loaded with the value xxx. At the end of the routine, the
values of R0 must be restored. See Section 10.12.3 in the DSP96002 User’s Manual
(DSP96002UM/AD) for an example.
1. Send command WRITE PDB REGISTER and GO (no EX).
(ODEC selects PDB as destination for serial data.)
2. ACK
3. Send the 32-bit opcode: “MOVEP P:(R0)+, x:OGDB”
(After the 32 bits have been received, the PDB register drives the PDB. ODEC releases the chip
from “halt” state and the MOVEM instruction is executed. This instruction does not change the
cache status in any way but the hit/miss mechanism is activated. The value of HIT/MISS signal
is sampled in bit 20 in the OSCR register. The signal that marks the end of the instruction returns
the chip to the “halt” state and an acknowledge is issued to the command controller.)
4. ACK
5. Send command READ OSCR REGISTER
(ODEC selects OSCR as the source for the serial data and an acknowledge is issued to the
command controller.)
6. ACK
7. CLK
8. Send command NO SELECTION and GO (no EX).
(ODEC releases the chip from the “halt” state and the instruction is executed again (in a
“REPEAT-like “fashion). The signal that marks the end of the instruction returns the chip to the
“halt” state and an acknowledge is issued to the command controller.)
9. ACK
10. Send command READ OSCR REGISTER
(ODEC selects OSCR as source for serial data and an acknowledge is issued to the command
controller.)
11. ACK
12. CLK
13. Repeat from step 8 until the entire cache area is examined. At the end of the process R0 should be
restored.
5.4.3 Displaying the Valid-bits of Specific Cache Locations Starting From
Address xxx, When in PRAM Mode
When in PRAM mode the MOVEM instruction would not activate the HIT/MISS mecha-
nism and therefore the value of the valid-bit would not be reflected in the HIT/MISS status
bit. Therefore, it is necessary to switch to cache mode before reading the valid-bits. Use
the following sequence to switch to cache mode: