Figure 2-9. bus handshake state diagram – Motorola DSP96002 User Manual
Page 21
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DSP96002 USER’S MANUAL
MOTOROLA
Likewise, when executing the read part of a RMW access, the end_of_sequence signal is deasserted.
This signal is used to give up bus ownership if
—
B
–
G is deasserted during bus transfers. The state ma-
chine which controls the bus handshake is illustrated in Figure 2.9.
The transition arcs are labeled by two letters which denote its source and destination states. The equa-
tions of the transition arcs are described as follows:
XX = ^ext_acc_req
& ^( ^
—
B
–
G &
—
B
–
B )
XY = ext_acc_req
& ^( ^
—
B
–
G &
—
B
–
B )
XZ = ext_acc_req
& ( ^
—
B
–
G &
—
B
–
B )
XW = ^ext_acc_req
& ( ^
—
B
–
G &
—
B
–
B )
YX = ^ext_acc_req
& ^( ^
—
B
–
G &
—
B
–
B )
(note 1)
YY = ext_acc_req
& ^( ^
—
B
–
G &
—
B
–
B )
YZ = ext_acc_req
& ( ^
—
B
–
G &
—
B
–
B )
YW = ^ext_acc_req
& ( ^
—
B
–
G &
—
B
–
B )
(note 1)
ZX = ^ext_acc_req
&
—
B
–
G
ZY = ext_acc_req
&
—
D
—
B
–
G & end_of_sequence
(note 3)
ACTIVE_
MASTER
(Z)
—
B
–
R = 0
—
B
–
A = 0
Figure 2-9. Bus Handshake State Diagram
REQUEST_BUS
(Y)
—
B
–
R = 0
—
B
–
A = 1
PARKING_
MASTER
(W)
—
B
–
R =
—
R
–
H
IDLE
(X)
—
B
–
R =
—
R
–
H
YY
XX
ZZ
WW
(delayed)
ZY
YZ
ZX
XZ
WY
(non-existant)
YX (illegal)
XY
ZW
WZ
WX
XW
(delayed
)
YW (illegal)