Motorola DSP96002 - Manual (Page 144)

8 - 4 DSP96002 USER’S MANUAL MOTOROLA
interrupt instructions are being fetched, the PC is inhibited from being updated. After the two interrupt
words have been fetched, the PC is used for any following instruction fetches.
After both interrupt instructions words have been fetched, they are guaranteed to be executed. This is true
even if the instruction that is currently being executed is a change of flow instruction (i.e., JMP, JSR, etc.)
that would normally ignore the instructions in the pipe. After the interrupt instruction fetch, the PC will point
to the instruction that would have been fetched if the interrupt instructions had not been substituted.
8.3.2 Interrupt Instruction Execution
Two types of interrupt routines may be used: fast and long. The fast routine consists of only the two auto-
matically inserted interrupt instruction words. These words can contain any single two-word instruction or
any two one-word instructions, except for restrictions listed in Section A.9.2.1. Interrupt instruction execu-
tion is considered to be fast if neither of the instructions of the interrupt service routine cause a change of
flow. A jump to subroutine within a fast interrupt routine forms a long interrupt. A long interrupt routine is
terminated with an RTI instruction to restore the PC and SR from the stack and return to normal program
execution. Hardware Reset is a special exception which will normally contain only a JMP instruction at the
exception start address.
8.3.2.1 Fast Interrupt Instruction Execution
Execution of a fast interrupt routine always follows the following rules:
1. Status is not saved during a fast interrupt routine; therefore, instructions which modify status
should not be used.
2. Fast interrupt routines are never interruptible.
3. The fast interrupt routine may contain any single two-word instruction or any two one-word in-
structions, except for restrictions listed in Section A.9.2.1.
4. If one of the instructions in the fast routine is a jump to subroutine, then a long interrupt routine
is formed.
5. The PC is never updated during a fast interrupt routine.
6. Normal instruction fetching resumes using the PC following the completion of the fast interrupt
routine.
Figure 8-3 illustrates the effect of a fast interrupt routine on the instruction pipeline.